In the fabrication of microelectronic components, a number of the steps involved, for instance, in preparing integrated circuit chips and the packaging for the chips (articles to which the chips are attached for electrical interfacing and/or protection), are etching processes. Accordingly, over the years, a number of vastly different types of etching processes to remove material, sometimes in selective areas, have been developed and are utilized to varying degrees. Moreover, the steps of etching different layers which constitute, for instance, the finished integrated circuit chip are among the most critical and crucial steps.
Silicon oxide layers such as those formed by reacting tetraethylorthosilicate (TEOS) and oxygen or ozone have been used as insulators especially where gap-filling considerations (i.e. filling gaps between pre-existing structures) are important. Such silicon oxide layers are often used in so-called interlevel dielectric (ILD) between metal interconnects of aluminum/copper or tungsten typically for back end of the line (BEOL) wiring. A general discussion of interlevel dielectrics can be found in "Fundamentals of Semiconductor Processing Technology" by ElKareh, Kluwer Academic Publishers, (1995), pages 565-571, which discussion is incorporated herein by reference. Moreover, silicon oxide layers and other insulators obtained by other processes may likewise be used as interlevel dielectrics. For example, other widely used materials for such purposes are boron and/or phosphorous doped silicate glasses.
In a formation of a conventional ILD oxide structure, a first layer of interlevel dielectric such as silicon oxide may be deposited on a surface having raised metal features (e.g., metal lines) by chemical vapor deposition (CVD) with the silicon oxide filling the gaps between the metal lines. This CVD step typically results in the formation of undesired voids between in the deposited oxide between the metal features. The silicon oxide over the horizontal (top) surfaces of the metal lines may then be removed by an anisotropic etch (e.g., sputter etching) to open the voids. The structure at this point typically has silicon oxide left in spaces between lines and as spacers on the sidewalls of the metal lines. A second layer of an insulator such as silicon oxide can then be deposited to fill the voids and complete the interlevel dielectric structure between different metallic layers.
In some instances, it may be desirable to replace certain components of an interlevel dielectric structure with alternative dielectric materials to modify the dielectric function of the ILD (e.g., by substituting a lower dielectric constant material) and/or to facilitate some other processing step or device construction. For example, the removal of oxide dielectric might be desired in order to form air bridge, air gap or other very low dielectric constant configurations. See for example, the formation of structures discussed in U.S. Pat. Nos. 4,985,990; 4,987,101; 5,308,440; 5,407,860; and 5,461,003, the disclosures of which are incorporated herein by reference.
The ability to economically and reliably form these various dielectric structures often depends on the ability to selectively remove silicon oxides especially where pre-exposed metal features are present or where metal features are to be exposed by the desired oxide removal. Thus, it is desired to obtain improved oxide removal processes which have improved performance capability and reliability. In addition to improving the manufacture of existing device structures, such improved processes would enable the commercial manufacture of structures which may not be practical using known techniques. The need for improved oxide removal processes increases with reduction in size of the metal features in the integrated circuit design.